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| INTEGRATED CIRCUITS DATA SHEET SAA7715H Digital Signal Processor Preliminary specification File under Integrated Circuits, IC01 2001 May 07 Philips Semiconductors Preliminary specification Digital Signal Processor CONTENTS 1 1.1 1.2 2 3 4 5 6 7 8 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.4 8.5 8.5.1 8.5.2 8.6 8.7 8.8 8.9 8.10 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 FEATURES Hardware Possible firmware APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION PLL division factors for different clock inputs The word select PLL The Filter Stream DAC (FSDAC) Interpolation filter Noise shaper Function of pin POM Power off plop suppression Pin VREFDA for internal reference Supply of the analog outputs External control pins Digital serial inputs/outputs and SPDIF inputs Digital serial inputs/outputs SPDIF inputs I2C-bus interface (pins SCL and SDA) Reset Power-down mode Power supply connection and EMC Test mode connections (pins TSCAN, RTCB and SHTCB) I2C-BUS PROTOCOL Addressing Slave address (pin A0) Write cycles Read cycles Program RAM Data word alignment I2C-bus memory map specification I2C-bus memory map definition Table definitions 10 10.1 10.1.1 10.2 10.2.1 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.3.7 10.4 10.4.1 10.4.2 10.4.3 10.4.4 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 18.5 19 20 21 22 SAA7715H SOFTWARE IN ROM DESCRIPTION Audio dynamics compressor Theory of operation Audio enhancer Theory of operation Equalizer General description Overview Controls Centre frequency Gain Q Hints and tips Stereo spatializer Overview Controls Mix Hints and tips LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS I2S-BUS TIMING I2C-BUS TIMING APPLICATION DIAGRAM PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS 2001 May 07 2 Philips Semiconductors Preliminary specification Digital Signal Processor 1 1.1 FEATURES Hardware SAA7715H * 24-bit Philips 70 MIPS DSP core (24-bit data path and 12/24-bit coefficient path) * 1.5 kbyte of downloadable DSP program memory (PRAM) * 2 kbyte of DSP program memory (PROM) * 2.5 kbyte of re-programmable DSP data memory (XRAM) * 512 byte of re-programmable DSP coefficient memory (YRAM) * Four stereo digital serial inputs (8 channels) with common BCK and WS. To these inputs the I2S-bus format or LSB-justified formats can be applied * One stereo bitstream DAC (2 channels) with 64 fold oversampling and noise shaping * Selectable clock output (pin SYSCLK) for external slave devices (512fs to 128fs) * Four stereo digital serial outputs (8 channels) with selectable I2S-bus or LSB-justified format * Two SPDIF inputs combined with digital serial input * On-board WS_PLL generates clock for on-board DAC and output pin SYSCLK * I2C-bus controlled (including fast mode) * Programmable Phase-Locked Loop (PLL) derives the clock for the DSP from the CLK_IN input * -40 to +85 C operating temperature range * supply voltage only 3.3 V * All digital inputs are tolerant for 5 V input levels * Power-down mode for low current consumption in standby mode * Optimized pinning for applications with other Philips DACs (such as UDA1334, UDA1355 and UDA1328). 1.2 Possible firmware * Incredible surround * Incredible mono (Imono) * DPL virtualiser * Dolby digital virtualiser (DVD post-processing) * Dynamic compressor * Spectral enhancer * Equalizer with peaking/shelving filters * DC filters * Bass/treble control * Dynamic loudness * Tone/noise generator * Graphical spectrum analyser * Configurable Delay Unit (DLU) * Sound steering/elevation for CAR applications * Sample Rate Conversion (SRC). 2 APPLICATIONS * As co-processor for a car radio DSP in a car radio application for additional acoustic enhancements (sound steering/sound elevation/signal processing) * Multichannel audio: in DVD and Home theatre applications as post-processing device like signal virtualisation (virtual 3D surround) and acoustic enhancement, tone control, volume control and equalizers * Multichannel decoding: Dolby Pro Logic and virtual 3D surround * PC/USB audio applications: stereo widening (Incredible surround), sound steering, sound positioning and speaker equalization. * Dolby(R)(1) Pro Logic decoding * Smoothed volume control (without zipper noise) * Automatic Volume Levelling (AVL) * Dynamic bass enhancement * Ultra bass (1) Dolby -- Available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA94111, USA, from whom licensing and application information must be obtained. Dolby is a registered trade-mark of Dolby Laboratories Licensing Corporation. 2001 May 07 3 Philips Semiconductors Preliminary specification Digital Signal Processor 3 GENERAL DESCRIPTION SAA7715H The SAA7715 can be configured for various audio applications by downloading the dedicated DSP program code into the DSP program RAM or using the ROM or a combination of both. During the `Power-down mode' the contents of the memories and all other settings will keep their values. The SAA7715 can be initialized using the I2C-bus interface. Several system application examples, based on this existing SAA7715, are available for a wide range of audio applications (e.g car radio DSP, DVD post-processing, Dolby Pro Logic, PC/USB audio and more) which can be used as a reference design for customers. The SAA7715 is a cost effective and powerful high performance 24-bit programmable DSP for a variety of digital audio applications. This DSP device integrates a 24-bit DSP core with programmable memories (program RAM/ROM, data and coefficient RAM), 4 digital serial inputs, 4 digital serial outputs, 2 separate SPDIF receivers, a stereo FSDAC, a standard Philips I2C-bus interface, a phase-locked loop for the DSP clock generation and a second phase-locked loop for system clock generation (internal and external DAC clocks). 4 QUICK REFERENCE DATA SYMBOL PARAMETER operating supply voltage CONDITIONS MIN. TYP. 3.3 95 20 380 400 MAX. 3.45 - - - - UNIT V mA mA mW A VDD IDDD IDDA Ptot IPOWERDOWN all pins VDD with respect to 3.15 pins VSS - - - - supply current of the digital high activity of the DSP at part DSPFREQ frequency supply current of the analog part total power dissipation DC supply current of the total chip in Power-down mode sample frequency total harmonic distortion-plus-noise to signal ratio of DAC signal-to-noise ratio of DAC clock input maximum DSP clock zero input and output signal high activity of the DSP at DSPFREQ frequency pin POWERDOWN enabled at IIS_WS1, SPDIF1 or SPDIF2 input at 0 dB at -60 dB code = 0 DIV_CLK_IN = LOW DIV_CLK_IN = HIGH fs (THD + N)/SDAC 32 - - - 8.192 16.384 - 44.1 -85 -37 100 96 - - - kHz dB(A) dB(A) dB(A) MHz MHz MHz S/NDAC CLK_IN DSPFREQ 5 11.2896 12.288 - - 24.576 70 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7715H QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm VERSION SOT307-2 2001 May 07 4 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 May 07 5 IIS_IN3 9 6 Philips Semiconductors Digital Signal Processor BLOCK DIAGRAM RESERVED1 RESERVED2 handbook, full pagewidth RESERVED3 SPDIF2 SPDIF1 VDDA1 VDDA2 VSSA1 VSSA2 VDDI1 24 1 2 3 5 25 4 7 8 VSSI1 14 VDDE VSSE 35 17 23 16 37 15 21 VSSI2 10 31 30 IIS_BCK1 IIS_WS1 IIS_IN1 IIS_IN4 IIS_OUT1 IIS_OUT2 IIS_OUT3 IIS_OUT4 IIS_BCK IIS_WS XRAM YRAM 29 28 33 SAA7715H IIS_IN2 6 32 DSP CORE 34 36 VOUTL VOUTR POM VREFDA /2 S PRAM PLL DSP CLOCK PROM STEREO DAC 256 fs CLOCK 39 38 TCB I2C-BUS WS_PLL 22 CLK_IN 41 DIV_CLK_IN 44 DSP_INOUT7 43 DSP_INOUT6 42 DSP_INOUT5 40 POWERDOWN 20 SHTCB 19 RTCB 26 TSCAN 13 SDA 12 SCL 11 A0 27 SYSCLK 18 DSP_RESET MGT826 Preliminary specification SAA7715H Fig.1 Block diagram. Philips Semiconductors Preliminary specification Digital Signal Processor 7 PINNING SYMBOL IIS_BCK1 IIS_WS1 IIS_IN1 RESERVED1 IIS_IN4 IIS_IN2 RESERVED2 RESERVED3 IIS_IN3 VSSI2 A0 SCL SDA VSSI1 VSSA2 VDDI1 VDDA2 DSP_RESET RTCB SHTCB VSSE CLK_IN VDDE SPDIF2 SPDIF1 TSCAN SYSCLK IIS_OUT4 IIS_OUT3 IIS_OUT2 IIS_OUT1 IIS_WS IIS_BCK VOUTL VDDA1 VOUTR VSSA1 VREFDA POM POWERDOWN 2001 May 07 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PIN TYPE ipthdt5v ipthdt5v ipthdt5v ipthdt5v ipthdt5v ipthdt5v ipthdt5v ipthdt5v ipthdt5v vssi ipthdt5v iptht5v iic400kt5v vssis vssco vddi vddco ipthut5v ipthdt5v ipthdt5v vsse iptht5v vdde apio apio ipthdt5v bpt4mthdt5v ops5c ops5c ops5c ops5c ops5c ops5c apio vddo apio vsso apio apio iptht5v DESCRIPTION SAA7715H bit clock signal belonging to data of digital serial inputs 1 to 4 word select signal belonging to data of digital serial inputs 1 to 4 data pin of digital serial input 1 not to be connected externally data pin of digital serial input 4 data pin of digital serial input 2 not to be connected externally not to be connected externally data pin of digital serial input 3 ground supply (core only) (bond out to 2 pads) slave sub-address I2C-bus selection/serial data input test control block clock input of I2C-bus data input/output of I2C-bus ground supply (core only) ground supply analog of PLL, WS_PLL, SPDIF input stage positive supply (core only) (bond out to 2 pads) positive supply analog of PLL, WS_PLL, SPDIF input stage general reset of chip (active LOW) asynchronous reset test control block, connect to ground (internal pull down) shift clock test control block (internal pull down) ground supply (peripheral cells only) system clock input positive supply (peripheral cells only) SPDIF2 data input (internally multiplexed with digital serial input 3) SPDIF1 data input (internally multiplexed with digital serial input 2) scan control active HIGH (internal pull down) n x fs output of SAA7715 data pin of digital serial output 4 data pin of digital serial output 3 data pin of digital serial output 2 data pin of digital serial output 1 word select output belonging to digital serial output 1 to 4 bit clock output belonging to digital serial output 1 to 4 analog left output pin. FSDAC positive supply voltage (bond out to 2 pads) analog right output pin FSDAC ground supply voltage (bond out to 2 pads) voltage reference pin of FSDAC power-on mute pin of FSDAC standby mode of chip 6 Philips Semiconductors Preliminary specification Digital Signal Processor SAA7715H SYMBOL DIV_CLK_IN DSP_INOUT5 DSP_INOUT6 DSP_INOUT7 Table 1 PIN 41 42 43 44 PIN TYPE ipthdt5v bpts5thdt5v bpts5thdt5v bpts5thdt5v DESCRIPTION divide the input frequency on pin CLK_IN by two digital input/output flag of the DSP-core (F5 of the status register) digital input/output flag of the DSP-core (F6 of the status register) digital input/output flag of the DSP-core (F7 of the status register) Brief explanation of used pin types EXPLANATION analog I/O pad cell; actually pin type vddco 43 MHz bidirectional pad; push-pull input; 3-state output; 5 ns slew rate control; TTL; hysteresis; pull-down; 5 V tolerant 43 MHz bidirectional pad; push-pull input; 3-state output; 5 ns slew rate control; TTL; hysteresis; 5 V tolerant bidirectional pad; push-pull input; 3-state output; 4 mA output drive; TTL; hysteresis; pull-down; 5 V tolerant I2C-bus pad; 400 kHz I2C-bus specification; 5 V tolerant input pad buffer; TTL; hysteresis; pull-down; 5 V tolerant input pad buffer; TTL; hysteresis; 5 V tolerant input pad buffer; TTL; hysteresis; pull-up; 5 V tolerant output pad; push-pull; 5 ns slew rate control; CMOS output pad; push-pull; 4 mA output drive VDD supply to core only VDD supply to peripheral only VDD supply to core only VDD supply to core only VSS supply to core only (vssco does not connect the substrate) VSS supply to peripheral only VSS supply to core and peripheral VSS supply to core only; with substrate connection VSS supply to core only PIN TYPE apio bpts5thdt5v bpts5tht5v bpt4mthdt5v iic400kt5v ipthdt5v iptht5v ipthut5v ops5c op4mc vddco vdde vddi vddo vssco vsse vssi vssis vsso 2001 May 07 7 Philips Semiconductors Preliminary specification Digital Signal Processor SAA7715H 42 DSP_INOUT5 44 DSP_INOUT7 43 DSP_INOUT6 handbook, full pagewidth 40 POWERDOWN 41 DIV_CLK_IN 38 VREFDA 36 VOUTR 34 VOUTL 35 VDDA1 37 VSSA1 39 POM IIS_BCK1 1 IIS_WS1 2 IIS_IN1 3 RESERVED1 4 IIS_IN4 5 IIS_IN2 6 RESERVED2 7 RESERVED3 8 IIS_IN3 9 VSSI2 10 A0 11 33 IIS_BCK 32 IIS_WS 31 IIS_OUT1 30 IIS_OUT2 29 IIS_OUT3 SAA7715H 28 IIS_OUT4 27 SYSCLK 26 TSCAN 25 SPDIF1 24 SPDIF2 23 VDDE VSSE 21 DSP_RESET 18 CLK_IN 22 SCL 12 SDA 13 VSSI1 14 VSSA2 15 VDDI1 16 VDDA2 17 RTCB 19 SHTCB 20 MGT827 Fig.2 Pin configuration. 2001 May 07 8 Philips Semiconductors Preliminary specification Digital Signal Processor 8 8.1 FUNCTIONAL DESCRIPTION PLL division factors for different clock inputs SAA7715H An on-chip PLL generates the clock for the DSP. The DSP runs at a selectable frequency of maximum 70 MHz. The clock is generated with the PLL that uses the CLK_IN of the chip to generate the DSP clock. Table 2 gives the division factors and the values of the DSP_TURBO and the DIV_CLK_IN bits that need to be set via I2C-bus (see Table 10). Table 2 PLL division factor per clock input. pll_div[4:0] 10H 09H 03H 00H 10H 0BH 09H 00H N 272 227 198 181 272 244 227 181 DSP_TURBO 1 1 1 1 1 1 1 1 DIV_CLK_IN 0 0 0 0 1 1 1 1 DSP_CLOCK (MHz) 69.632 69.008 69.854 69.504 69.632 68.544 69.008 69.504 CLOCK INPUT (MHz) 8.192 (32 kHz x 256) 9.728 (38 kHz x 256) 11.2896 (44.1 kHz x 256) 12.288 (48 kHz x 256) 16.384 (32 kHz x 512) 18.432 (32 kHz x 576) 19.456 (38 kHz x 512) 24.576 (96 kHz x 256) The above table does NOT imply that the clock input is restricted to the values given in this table. The clock input is restricted to be within the range of 8.192 to 12.228 MHz. For higher clock frequencies pin DIV_CLK_IN should be set to logic 1 performing a divide by 2 of the CLK_IN signal and thereby doubling the CLK_IN frequency range that is allowed (16.384 to 24.576 MHz). 8.2 The word select PLL A second on-chip PLL generates a selectable multiple of the sample rate frequency supplied on the word select pin IIS_WS (= IIS_WS1). The clock generated by this so called WS_PLL is available for the user at pin SYSCLK. Tables 3 and 4 show the I2C-bus settings needed to generate the n x fs clock. The memory map of the I2C-bus bits is shown in Table 10. Table 3 Word select input range selection SAMPLE RATE OF fs (kHz) 32 to 50 50 to 96 Table 4 Selection of n x fs clock at SYSCLK output sel1 0 1 1 0 0 sel0 0 1 0 1 0 SYSCLK (n x IIS_WS1) 512 384 256 192 128 DUTY FACTOR 50% for 32 to 50 kHz input; 66% for 50 to 96 kHz input 50% 50% 50% 50% sel_loop_div[1:0] 01 00 sel2 1 0 0 0 0 2001 May 07 9 Philips Semiconductors Preliminary specification Digital Signal Processor 8.3 The Filter Stream DAC (FSDAC) 8.3.4 SAA7715H POWER OFF PLOP SUPPRESSION The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC scales proportionally with the power supply voltage. 8.3.1 INTERPOLATION FILTER To avoid plops in a power amplifier, the supply voltage of the analog part of the DAC and the rest of the chip can be fed from a separate supply of 3.3 V. A capacitor connected to this supply enables to provide power to the analog part at the moment the digital voltage is switching off fast. In this event the output voltage will decrease gradually allowing the power amplifier some extra time to switch off without audible plops. 8.3.5 PIN VREFDA FOR INTERNAL REFERENCE The digital filter interpolates from 1 to 64fs by means of a cascade of a recursive filter and an FIR filter. Table 5 Digital interpolation filter characteristics CONDITIONS 0 to 0.45fs >0.55fs 0 to 0.45fs DC NOISE SHAPER VALUE (dB) 0.03 -50 116.5 -3.5 With two internal resistors half the supply voltage VDDA1 is obtained and used as an internal reference. This reference voltage is used as DC voltage for the output operational amplifiers and as reference for the DAC. In order to obtain the lowest noise and to have the best ripple rejection, a filter capacitor has to be added between this pin and ground, preferably close to the analog pin VSSA1. 8.3.6 SUPPLY OF THE ANALOG OUTPUTS ITEM Pass band ripple Stop band Dynamic range Gain 8.3.2 The entire analog circuitry of the DACs and the OPAMPS are supplied by 2 supply pins, VDDA1 and VSSA1. The VDDA1 must have sufficient decoupling to prevent THD degradation and to ensure a good Power Supply Rejection Ratio (PSRR). The digital part of the DAC is fully supplied from the chip core supply. 8.4 External control pins The 5th-order noise shaper operates at 64fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter. 8.3.3 FUNCTION OF PIN POM The flags DSP_INOUT5 to DSP_INOUT7 are available as external pins. The flags can be used by the DSP depending on the downloaded software. With pin POM it is possible to switch off the reference current of the DAC. The capacitor on pin POM determines the time after which this current has a soft switch-on. So at power-on the current audio signal outputs are always muted. The loading of the external capacitor is done in two stages via two different current sources. The loading starts at a current level that is lower than the current loading after the voltage on pin POM has passed a particular level. This results in an almost dB-linear behaviour. This prevents `plop' effects during power on/off. 2001 May 07 10 Philips Semiconductors Preliminary specification Digital Signal Processor 8.5 8.5.1 Digital serial inputs/outputs and SPDIF inputs DIGITAL SERIAL INPUTS/OUTPUTS 8.5.2 SPDIF INPUTS SAA7715H For communication with external digital sources a digital serial bus is implemented. It is a serial 3-line bus, having one line for data, one line for clock and one line for the word select. For external digital sources the SAA7715 acts as a slave, so the external source is master and supplies the clock. For the I2S-bus format itself see the official specification from Philips. The digital serial input is capable of handling Philips I2S-bus and LSB-justified formats of 16, 18, 20 and 24 bits word sizes. The sampling frequency can be 32 up to 96 kHz. See the I2C-bus memory map for the bits that must be programmed, for selection of the desired serial format. See Fig.3 for the general waveforms of the possible formats. When the applied word length exceeds 24 bits, the LSBs are skipped. The digital serial input/output circuitry is limited in handling the number of BCK pulses per WS period. The maximum allowed number of bit clocks per WS period is 256. Also the number of bit clocks during WS LOW and HIGH must be equal (50% WS duty factor) only for the LSB-justified formats. There are two modes in which the digital inputs can be used (the mode is selectable via an I2C-bus bit): * Use up to 4 digital serial inputs (8ch) with common WS and BCK signal (8ch IN and 8ch OUT + 2ch FSDAC output) * Use one of the 2 SPDIF inputs as source instead of the use of the digital serial inputs (2ch IN and 8ch OUT + One 2ch FSDAC output). Two separate SPDIF receivers are available, one shared with digital serial input 2 (SPDIF1) and one with the digital serial input 3 (SPDIF2). The sample frequency at which the SPDIF inputs can be used must be in the range of 32 to 96 kHz. There are few control signals available from the SPDIF input stage. These are connected to flags of the DSP: * A lock signal indicating if the SPDIF input 1 or 2 is in lock * The pcm_audio/non-pcm_audio bit indicating if an audio or data stream is detected on SPDIF input 1 or 2. The FSDAC output will NOT be muted in the event of non-audio PCM stream. This status bit can be read via the I2C-bus, the microprocessor controller can decide to put the DAC into MUTE (via pin POM). Handling of channel status bits: The first 40 (of 192) channel status bits of the selected SPDIF source (0FFBH, bit 20), will come available in the I2C-bus registers 0FF2H to 0FF5H. Two registers 0FF2H to 0FF3H contain the information for the right channel, the other two (0FF4H to 0FF5H) contain the information for the left channel. The information can be read via I2C-bus or by the DSP program. The design fulfils the digital audio interface specification "IEC 60958-1 Ed2, part 1, general part IEC 60958-3 Ed2, part 3, consumer applications". 2001 May 07 11 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 May 07 12 DATA MSB B2 B3 B4 B17 LSB LSB-JUSTIFIED FORMAT 18 BITS MSB B2 B3 B4 B17 LSB WS LEFT 20 BCK 19 18 17 16 15 2 1 RIGHT 20 19 18 17 16 15 2 1 DATA MSB B2 B3 B4 B5 B6 B19 LSB LSB-JUSTIFIED FORMAT 20 BITS MSB B2 B3 B4 B5 B6 B19 LSB WS 24 BCK 23 22 21 LEFT 20 19 18 17 16 15 2 1 24 23 22 21 RIGHT 20 19 18 17 16 15 2 1 Philips Semiconductors handbook, full pagewidth Digital Signal Processor WS 1 BCK 2 3 LEFT >=8 1 2 3 RIGHT >=8 DATA MSB B2 MSB B2 MSB INPUT FORMAT I2S-BUS WS LEFT 16 15 2 1 RIGHT 16 15 2 1 BCK DATA MSB B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS MSB B2 B15 LSB WS LEFT 18 17 16 15 2 1 RIGHT 18 17 16 15 2 1 BCK Preliminary specification SAA7715H DATA MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB LSB-JUSTIFIED FORMAT 24 BITS MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB MGR751 Fig.3 All serial data input/output formats. Philips Semiconductors Preliminary specification Digital Signal Processor 8.6 I2C-bus interface (pins SCL and SDA) SAA7715H The reset sets all I2C-bus bits to their default value and it restarts the DSP program. 8.8 Power-down mode The I2C-bus format is described in "The I2C-bus and how to use it", order no. 9398 393 40011. For the external control of the SAA7715 a fast is implemented. This is a 400 kHz bus which is downward compatible with the standard 100 kHz bus. There are two different types of control instructions: * Loading of the Program RAM (PRAM) with the required DSP program - Programming the coefficient RAM (YRAM) - Instructions to control the DSP program. * Selection of the digital serial input/output format to be used, the DSP clock speed. The detailed description of the I2C-bus and the description of the different bits in the memory map is given in Chapter 9. 8.7 Reset I2C-bus The Power-down mode switches off all activity on the chip. The Power-down mode can be switched on and off using pin POWERDOWN. This pin needs to be connected to ground if not used. The following applies for the Power-down mode: * Power-down mode may only be switched on when there is no I2C-bus activity to or from the SAA7715 * Power-down mode may not be switched on before the complete chip has been reset (DSP_RESET active LOW) * The clock signal on pin CLK_IN should be running during Power-down mode * It is advised to set pin POM to logic 0 before switching on the Power-down mode and set it back to logic 1 after the chip actually returns from Power-down mode as shown in Fig.4 * All on-chip registers and memories will keep their values during Power-down mode * Digital serial outputs are not muted, the last value is kept on the output * The SAA7715 will not `lock-up' the I2C-bus during Power-down mode (SDA line). Figure 4 shows the time the chip actually is in Power-down mode after switching on/off pin POWERDOWN. The reset (pin DSP_RESET) is active LOW and needs an external 22 k pull-up resistor. Between this pin and the VSSI ground a capacitor of 1 F should be connected to allow a proper switch-on of the supply voltage. The capacitor value is such that the chip is in reset as long as the power supply is not stabilized. A more or less fixed relationship between the DSP reset and the POM time constant is obligatory. The voltage on pin POM determines the current flowing in the DACs. handbook, full pagewidth CLK_IN POWERDOWN device actually in Power-down mode tA POM MGT828 tB tA = 4 x (256/CLK_IN); 8.192 MHz < CLK_IN < 12.288 MHz. tA = 4 x (512/CLK_IN); 16.384 MHz < CLK_IN < 24.576 MHz. tB = 128 x (256/CLK_IN); 8.192 MHz < CLK_IN < 12.288 MHz. tB = 128 x (512/CLK_IN); 16.384 MHz < CLK_IN < 24.576 MHz. Fig.4 Power-down mode. 2001 May 07 13 Philips Semiconductors Preliminary specification Digital Signal Processor 8.9 Power supply connection and EMC SAA7715H DSP for manipulating the data and coefficients. More details can be found in the I2C-bus memory map, see Table 8. The data length is 2, 3 or 4 bytes depending on the accessed memory. If the Y-memory is addressed the data length is 2 bytes, in the event of the X-memory the length is 3 bytes. The slave receiver detects the address and adjusts the number of bytes accordingly. For this RAM-based product the internal P-memory (PRAM) can be accessed via the I2C-bus interface. The transmitted data-stream should be 4 bytes. 9.4 Read cycles The digital part of the chip has in total 4 positive supply line connections and 5 ground connections. To minimize radiation the chip should be put on a double layer printed-circuit board with on one side a large ground plane. The ground supply lines should have a short connection to this ground plane. A coil/capacitor network in the positive supply line of the peripheral power supply line can be used as high frequency filter. The core supply lines (VDDI) have an on-chip decoupling capacitance, for EMC reasons an external decoupling capacitance must not be used on this pin. A series resistor plus capacitance is required for proper operation on pin VDDA2, see Fig.11. 8.10 Test mode connections (pins TSCAN, RTCB and SHTCB) Pins TSCAN, RTCB and SHTCB are used to put the chip in test mode and to test the internal connections. Each pin has an internal pull-down resistor to ground. In the application these pins can be left open or connected to ground. 9 9.1 I2C-BUS PROTOCOL Addressing The I2C-bus configuration for a read cycle is shown in Fig.6. The read cycle is used to read the data values from XRAM, YRAM or PRAM. The master starts with a START condition S, the SAA7715 address `0011110' and a logic 0 (write) for the read/write bit. This is followed by an acknowledge of the SAA7715. Then the master writes the high memory address (ADDR H) and low memory address (ADDR L) where the reading of the memory content of the SAA7715 must start. The SAA7715 acknowledges these addresses both. The master generates a repeated START (Sr) and again the SAA7715 address `0011110' but this time followed by a logic 1 (read) of the read/write bit. From this moment on the SAA7715 will send the memory content in groups of 3 (X/Y-memory or registers) or 4 (P-memory) bytes to the I2C-bus each time acknowledged by the master. The master stops this cycle by generating a negative acknowledge, then the SAA7715 frees the I2C-bus and the master can generate a STOP condition. The data is transferred from the DSP register to the I2C-bus register at execution of the MPI instruction in the DSP program. Therefore at least once every DSP routine an MPI instruction should be added. Before any data is transmitted on the I2C-bus, the device that should respond is addressed first. The addressing is always done with the first byte transmitted after the start procedure. 9.2 Slave address (pin A0) The SAA7715 acts as slave receiver or a slave transmitter. Therefore the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The slave address is shown in Table 6. Table 6 MSB 0 0 1 1 1 1 A0 Slave address LSB R/W The sub-address bit A0 corresponds to the hardware address pin A0 which allows the device to have 2 different addresses. The A0 input is also used in test mode as serial input of the test control block. 9.3 Write cycles The I2C-bus configuration for a write cycle is shown in Fig.5. The write cycle is used to write the bytes to the 2001 May 07 14 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 May 07 A Philips Semiconductors Digital Signal Processor S00111100C K ADDR H A C K ADDR L A C K DATA 1 A C K DATA ... A C K DATA 4 A CP K auto increment if repeated n-groups of 2, 3 or 4 bytes address R/W MGU331 S = START condition. P = STOP condition. ACK = acknowledge from SAA7715. ADDR H and ADDR L = address DSP register. DATA 1 to DATA 4 = 2, 3 or 4 bytes data word. Fig.5 Master transmitter writes to the SAA7715 registers. 15 A S00111100C K ADDR H A C K ADDR L A A S00111101C C r K K DATA 1 A C K DATA ... A C K DATA 4 A N CR AP K auto increment if repeated n-groups of 2, 3 or 4 bytes address R/W R/W MGU330 S = START condition. Sr = repeated START condition. P = STOP condition. ACK = acknowledge from SAA7715 (SDA LOW). R = repeat n-times the 2, 3 or 4 bytes data group. NA = Negative Acknowledge master (SDA HIGH). ADDR H and ADDR L = address DSP register. DATA 1 to DATA 4 = 2, 3 or 4 bytes data word. Preliminary specification SAA7715H Fig.6 Master transmitter reads from the SAA7715 registers. Philips Semiconductors Preliminary specification Digital Signal Processor 9.5 Program RAM SAA7715H The DSP has an instruction word width of 32 bits which means that this space should be accessed with 4 bytes in consecutive order and does have the auto-increment function. 9.6 Data word alignment The SAA7715 has a 1.5 kbyte PRAM to store the DSP instruction code into. Also a 2 kbyte PROM is on-chip available and can be accessed (memory mapped) without the need of selecting the PROM or PRAM. The DSP instruction code can be downloaded into the PRAM via the I2C-bus. The write and read cycle are shown in Figs 5 and 6 respectively. It is possible to transfer data via the I2C-bus to a destination where it can have different data word length. Those destinations with data word are shown in Table 7. Table 7 Data word alignment DESTINATION DSP-PRAM DSP and general control I2C-bus registers DSP-XRAM DSP-YRAM DATA WORD MBBB BBBB BBBB BBBB BBBB BBBB BBBB BBBL MBBB BBBB BBBB BBBB BBBB BBBL MBBB BBBB BBBB BBBB BBBB BBBL MBBB BBBB BBBB BBBB BBBB BBBL XXXX MBBB BBBB BBBL BYTES (NUMBER) 4 3 3 3 2 SOURCE I2C-bus I2C-bus I2C-bus I2C-bus I2C-bus 2001 May 07 16 Philips Semiconductors Preliminary specification Digital Signal Processor 9.7 I2C-bus memory map specification SAA7715H The I2C-bus memory map contains all defined I2C-bus bits. The map is split up in two different sections: the hardware memory registers and the RAM definitions. In Table 8 the preliminary memory map is depicted. The hardware registers are memory map on the XRAM of DSP. Table 9 shows the detailed memory map of those locations. All locations are acknowledged by the SAA7715 even if the user tries to write to a reserved space. The data in these sections will be lost. Reading from these locations will result in undefined data words. Table 8 I2C-bus memory map ADDRESS 8000H to 87FFH 602FH 2000H to 25FFH 1000H to 01FFH 0FF2H to 0FF5H, 0FFBH 0000H to 09FFH Table 9 FUNCTION DSP to PROM (not readable via I2C-bus) DSP and general control DSP to PRAM DSP to YRAM I2C-bus register DSP to XRAM 2k x 32 bits 1 x 24 bits 1.5k x 32 bits 512 x 12 bits 1 x 24 bits 2.5k x 24 bits SIZE I2C-bus memory map overview ADDRESS DESCRIPTION Hardware registers 0FFBH 0FF5H 0FF4H 0FF3H 0FF2H DSP control 602FH DSP and general control register Selector register 1 SPDIF IN channel status register 1 left SPDIF IN channel status register 2 left SPDIF IN channel status register 1 right SPDIF IN channel status register 2 right 2001 May 07 17 Philips Semiconductors Preliminary specification Digital Signal Processor 9.8 I2C-bus memory map definition SAA7715H Table 10 DSP and general control register (602FH) NAME SIZE (BITS) 1 pll_div[4:0] dsp_turbo 5 1 reserved PLL clock division factor according to Table 2 PLL output frequency 1: double 0: no doubling 1 pc_reset_dsp 1 reserved program counter reset DSP 1: reset on 0: reset off 2 sel[2:0] sel_loop_div[1:0] 3 2 2 sel_FSDAC_clk 2 reserved selection of n x fs clock at SYSCLK output according to Table 4 word select input range selection for WS_PLL according to Table 3 reserved clock source for FSDAC 00: WS_PLL if no signal to pin CLK_IN 01: 512fs to pin CLK_IN 11: 256fs to pin CLK_IN dis_SYSCLK 1 output on pin SYSCLK 1: disable 0: enable 256fs_n*Fs 1 signal on pin SYSCLK 1: fixed 256fs clock 0: n x fs clock; determined by bits 13 to 11 1 reserved 0 23 to 22 0 21 0 20 00 010 01 00 00 10 to 9 13 to 11 15 to 14 17 to 16 19 to 18 1 0 7 8 DESCRIPTION DEFAULT 0 00011 1 BIT POSITION 0 5 to 1 6 Table 11 SPDIF IN channel status register 2 right (0FF2H) NAME ch_stat_in right lsb SIZE (BITS) 20 DESCRIPTION channel status SPDIF in right LSB bits 19 to 0 DEFAULT 00000H BIT POSITION 19 to 0 Table 12 SPDIF IN channel status register 1 right (0FF3H) NAME ch_stat_in right msb SIZE (BITS) 20 DESCRIPTION channel status SPDIF in right MSB bits 39 to 20 DEFAULT 00000H BIT POSITION 19 to 0 2001 May 07 18 Philips Semiconductors Preliminary specification Digital Signal Processor Table 13 SPDIF IN channel status register 2 left (0FF4H) NAME ch_stat_in left lsb SIZE (BITS) 20 DESCRIPTION channel status SPDIF in2 left LSB bits 19 to 0 SAA7715H DEFAULT 00000H BIT POSITION 19 to 0 Table 14 SPDIF IN channel status register 1 left (0FF5H) NAME ch_stat_in left msb SIZE (BITS) 20 DESCRIPTION channel status SPDIF in2 left MSB bits 39 to 20 DEFAULT 00000H BIT POSITION 19 to 0 Table 15 Selector register 1 (0FFBH) NAME format_in1 format_in2 format_in3 format_out en_output SIZE (BITS) 3 3 3 3 1 DESCRIPTION digital serial inputs 1 and 4 data format according to Table 17 digital serial input 2 data format according to Table 17 digital serial input 3 data format according to Table 17 digital serial outputs 1 to 4 data format according to Table 18 enable or disable digital serial outputs 1: enable 0: disable 1 master_source 4 reserved source selection 0000: digital serial input 1 0101: digital serial input 2 or SPDIF 1 (see bit 18) 1010: digital serial input 3 or SPDIF 2 (see bit 19) all other values are reserved spdif_sel1 1 SPDIF1 or digital serial input 2 1: SPDIF1 0: digital serial input 2 spdif_sel2 1 SPDIF2 or digital serial input 3 1: SPDIF2 0: digital serial input 3 sel_spdifin_chstat 1 select channel status information taken from SPDIF1 or SPDIF2 1: from input SPDIF2 0: from input SPDIF1 3 reserved 000 21 to 23 0 20 0 19 0 18 0 0000 13 14 to 17 DEFAULT 011 011 011 000 1 BIT POSITION 2 to 0 5 to 3 8 to 6 11 to 9 12 2001 May 07 19 Philips Semiconductors Preliminary specification Digital Signal Processor Table 16 Default settings of I2C-bus registers after power-up and reset I2C-BUS ADDRESS 602FH 0FFBH 0FF5H 0FF4H 0FF3H 0FF2H 9.9 Table definitions DEFAULT VALUE 0050C6H 0010DBH 000000H 000000H 000000H 000000H SAA7715H Table 17 Digital serial format for inputs 1 to 4 FORMAT_IN 1, 2 AND 3 OUTPUT BIT 2 0 1 1 1 1 BIT 1 1 0 0 1 1 BIT 0 1 0 1 0 1 standard I2S-bus LSB-justified, 16 bits LSB-justified, 18 bits LSB-justified, 20 bits LSB-justified, 24 bits Table 18 Digital serial formats for outputs 1 to 4 FORMAT_OUT OUTPUT BIT 2 0 1 1 1 1 BIT 1 0 0 0 1 1 BIT 0 0 0 1 0 1 standard I2S-bus LSB-justified, 16 bits LSB-justified, 18 bits LSB-justified, 20 bits LSB-justified, 24 bits The behaviour of a dynamics compressor is very similar to that of an Automatic Gain Control (AGC), the central idea being to scale the input signal by a slowly varying gain factor that is in turn regulated by the level of the input signal. The essential concepts are summed up nicely by Fig.7. Here we observe that when the input level exceeds a selected threshold, gain reduction is brought to bear according to the selected compression ratio, while signals appearing below the threshold are passed with unity gain. The net effect, therefore, is to compress the louder passages of source material. 10 SOFTWARE IN ROM DESCRIPTION 10.1 10.1.1 Audio dynamics compressor THEORY OF OPERATION The objective of a dynamics compressor is to reduce the dynamic range of the input signal for purposes of accommodating downstream devices, or simply to give the audio signal a different character. Early compressors were used primarily for limiting signals destined for recording on media with limited dynamic range. In the present day, compressors are routinely used in recording studios and in live performances to enhance the presence of various signals. 2001 May 07 20 Philips Semiconductors Preliminary specification Digital Signal Processor Ironically, most people think in terms of boosting the low signals when talking about dynamics compression. In fact, this is what actually happens after the output is rescaled to account for the gain reduction imposed by the current settings. By doing this the output signal can be forced to carry more power than the input. This is what gives the compressor its `punch' quality, for a more `in your face' sort of sound. Figure 8 shows an example of the transfer curves before and after application of output gain. Users should be aware, however, that abuse of output gain can amplify system noise to intolerable levels. SAA7715H 10.1.1.1 Control parameters Common to most compressors are five control parameters used for adjusting the behaviour of the compressor. These are typically labelled as threshold, ratio, attack time, release time, and output. By careful adjustment of these controls a skilled user can produce very pleasing results for a wide variety input source material. In the following subsections, functionality of each control is described. 10.1.1.2 Fixed versus variable mode handbook, halfpage output level (dB) no compression slope = 1/2 2:1 compression 4:1 compression 10:1 compression (limiting) The compressor module can be operated in so-called `fixed' mode or `variable' mode. When in variable mode, the user has full control over both the threshold and ratio controls. In fixed mode, controls are frozen and the effect operates at a fixed ratio of 2:1, with a threshold setting of -36 dB(FS). These settings were chosen as a good compromise for a wide variety of source material. 10.1.1.3 Threshold Threshold determines the level at which gain reduction begins. For example, if the threshold is set at -10 dB(FS), this means that all signals below -10 dB(FS) will be passed unaltered. Only when the input level exceeds this threshold is gain reduction (compression) brought to bear. Many times a dramatic change in the threshold setting will call for a ratio adjustment. Experiment with these two controls to find what works best for your system, your music, and most importantly, your ears. threshold input level (dB) MGT829 Fig.7 Gain reduction is applied only when the signal exceeds the set threshold level. 10.1.1.4 Ratio handbook, halfpage output level (dB) output gain 4:1 compression The ratio control sets the desired compression ratio. Settings are traditionally expressed in ratios such as 1.5:1, 2:1, 4:1, 10:1, etc. An explanation of how to interpret these settings is best served by example. Say we are dealing with a ratio of 1.5:1. This means that for every 1.5 dB increase in input level beyond the threshold, only 1 dB is passed to the output. Another way of explaining this is in terms of gain reduction. In this particular case a 0.5 dB gain reduction is imposed for every 1.5 dB increase beyond the threshold level. Compression ratio is changed by selecting one of the values in the drop-down list labelled `Ratio'. To increase the amount of compression, select one of the higher ratios. For a more subtle effect, select a lower setting, such as 1.5:1. threshold input level (dB) MGT830 Fig.8 Output gain can be used to restore the peak level to its maximum. 2001 May 07 21 Philips Semiconductors Preliminary specification Digital Signal Processor 10.1.1.5 Attack time SAA7715H The enhancer is also a very effective means of improving the sound of CD-quality audio, by restoring the presence and brilliance of the original acoustic performance. Attack time controls the rate at which gain-reduction is engaged following the detection of the input signal exceeding the threshold level. Typical values are in the range of 0 to 100 ms. Fast attack times tend to smooth out abrupt transients thereby helping to ensure the output level remains fairly consistent; however, at the same time fast attack times can easily destroy much of the dynamic character of sources having very distinguished attack transients (such as a piano or an acoustic guitar). Slow attack times, on the other hand, allow the sources attack transients to pass through virtually unaltered, thereby retaining most of the dynamic signature of the source. The danger here, however, is the possibility of clipping the output, or overloading one or more downstream components. The present implementation of the compressor does not provide user access to attack time. 10.2.1.1 Control parameters The enhancer has a single mix control, which determines the amount of generated harmonics to be added to the signal. High settings will result in a brighter effect with greater depth. For particularly dull audio, such as is often received over the Internet, a high mix level will have a pleasing effect. Intermediate settings are appropriate for CD-quality audio, although classical music listeners may prefer to use the enhancer sparingly. 10.3 10.3.1 Equalizer GENERAL DESCRIPTION * 2-channels * 5-bands * Control range: 20 Hz to 20 kHz. 10.3.2 OVERVIEW 10.1.1.6 Release time Complementing the attack time control, release time controls the speed at which the compressor disengages after the input level falls back below the threshold. Typical values here range from around 100 ms to several seconds. The present implementation of the compressor does not provide user access to release time. 10.1.1.7 Output or `make-up gain' In order to make maximum use of the available bit resolution, it becomes necessary to boost the compressors output in order to ensure the signal swings close to the maximum excursions allowed by the digital output. Notice in Fig.7 how the output level can be dramatically reduced, particularly at low threshold levels and high compression ratios. In the present implementation, this rescaling is managed automatically according to the current threshold and ratio settings. 10.2 10.2.1 Audio enhancer THEORY OF OPERATION The fundamental ideal for any high-fidelity audio rendering system is to reproduce the aural experience present at the time and place the original audio material was recorded. Unfortunately, practically all systems fall short of this ideal to some degree for a number of reasons. While environmental acoustics can play a significant role, in many cases performance deficiencies associated with the loudspeakers cause most of the `distortion'. This happens when the loudspeakers cannot deliver a uniform frequency response over the entire audio range (20 Hz to 20 kHz). Equalizers were invented to deal with frequency response problems by boosting or cutting selected frequency bands in the signal. Used in the right manner, a properly adjusted equalizer can effectively compensate for loudspeaker performance deficiencies, or any other frequency dependent amplitude variations in the system. Additionally, equalization can be used to create a customized frequency response which is better suited for a particular listener or a particular style of music, for instance. The type of equalizer provided with this system is of the parametric variety. Parametric equalizers differ from graphic equalizers by giving the user more control over the filters that actually effect the boost or cut of a particular band. More specifically, for each band, users can control the band's centre frequency, and also the width of the band of frequencies that are affected. The enhancer uses non-linear processing to generate extra harmonics, which are added to the audio to improve high frequency detail. It is particularly useful with streaming audio from the Internet, which is typically compressed to the extent that the original high frequency content is lost. 2001 May 07 22 Philips Semiconductors Preliminary specification Digital Signal Processor 10.3.3 CONTROLS 10.4 10.4.1 Stereo spatializer OVERVIEW SAA7715H The equalizer module exposes three controls for each of the five bands. These are referred to as gain, centre frequency, and Q. The gain control sets the amount of boost or cut applied to the particular band of frequencies. Centre frequency controls the frequency at which the boost or cut filter is centred, while the Q control determines the bandwidth (the range of frequencies) over which the filter operates. 10.3.4 CENTRE FREQUENCY In PC listening settings, the quality of the stereo image is sometimes compromised by the short distance between the loudspeakers, and also by the physical limitations of the loudspeakers themselves. The spatializer effect remedies these shortcomings by applying perceptually tuned signal-processing to create the illusion of a wider and more enveloping sound stage. Users should be relieved to know that relative positioning of instruments in the original material is preserved. In other words, tracks that are centre mixed in the original material remain centred; tracks panned left or right in the original mix remain left and right panned. The main difference is in the apparent width and depth of the sound stage, it is as though the listener is hearing a larger and more distant pair of speakers, spaced much farther apart than those actually present. 10.4.2 CONTROLS Centre frequency defines the frequency where boost or cut will be centred. To set the centre frequency, select the entry box and type in a number that is within the allowed range. 10.3.5 GAIN Use the gain control to adjust the amount or boost or cut. Move the slider upward (above the 0 dB line) to add boost, downward (below the 0 dB line) to cut. 10.3.6 Q The spatializer effect uses only one control to change its behaviour. 10.4.3 MIX The Q parameter determines the sharpness of the filter. As the value of Q increases, the filter becomes narrower, thereby reducing the filters effective bandwidth. High Q filters are useful for reducing speaker resonances, or for eliminating resonance that may be caused by the acoustic environment. Low Q filters, on the other hand, are useful for operating on a broad range of frequencies. 10.3.7 HINTS AND TIPS The mix control sets the intensity of the effect. Control is straight-forward. Add more effect by pulling the slider upward; move the slider downward to reduce the amount of effect. 10.4.4 HINTS AND TIPS Avoid using the equalizer for volume control. This is not the purpose of an equalizer. Remember, you are only trying to correct frequency response deviations from some `ideal' response that are due to loudspeaker deficiencies and perhaps the surrounding environment. Therefore you should strive to introduce the minimum amount of equalization that causes the system output to reach your desired response. Avoid excessive boost or cut. This can introduce noticeable coloration of the program material. Try a mix setting of about 0.7 as a starting point. For best results, position yourself between the speakers and a couple of feet back. Ideally, your ears should be at about the same level as the speakers, but this is not so critical. 2001 May 07 23 Philips Semiconductors Preliminary specification Digital Signal Processor 11 LIMITING VALUES In accordance with the Absolute Maximum Ratings System (IEC 60134). SYMBOL VDD VI IIK IOK IO(sink/source) IDD,ISS Tamb Tstg VESD Ilu(prot) Ptot Notes 1. Machine model (R = 0 ; C = 100 pF; L = 2.5 H). 2. Human body model (R = 1500 ; C = 100 pF). 12 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS mounted on printed-circuit board PARAMETER supply voltage input voltage input clamping diode current output clamping diode current output source or sink current VDD or VSS current per supply pin ambient temperature storage temperature electrostatic handling voltage latch-up protection current total power dissipation note 1 note 2 CIC specification/test method VI < - 0.5 V or VI > VDD + 0.5 V VO < - 0.5 V or VO > VDD + 0.5 V -0.5 V < VO < VDD + 0.5 V CONDITIONS SAA7715H MIN. -0.5 -0.5 - - - - -40 -65 200 2000 100 - MAX. +3.6 +5.5 10 20 20 50 +85 +125 - - - 600 UNIT V V mA mA mA mA C C V V mA mW VALUE 60 UNIT K/W 2001 May 07 24 Philips Semiconductors Preliminary specification Digital Signal Processor 13 CHARACTERISTICS VDD = 3.15 to 3.45 V; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. SAA7715H MAX. UNIT Supplies; Tamb = -40 to +85 C VDD IDDD IDDD(core) operating supply voltage supply current of the digital part supply current of the digital core part supply current of the digital periphery part supply current of the analog part supply current of the DAC high activity of the DSP at DSPFREQ frequency no external load to ground zero input and output signal zero input and output signal Power-down mode IDDA(SPDIF) Ptot IPOWERDOWN supply current of the SPDIF inputs, on-chip PLL and WSPLL total power dissipation DC supply current of the total chip in Power-down mode pin POWERDOWN enabled zero input and output signals all pins VDD with respect to pins VSS 3.15 - - 3.3 95 90 3.45 - - V mA mA IDDD(peri) IDDA IDDA(DAC) - - - - - - - 5 20 6.5 250 13.5 380 400 - - 13 - 27 - - mA mA mA A mA mW A Digital I/O; Tamb = -40 to +85 C; VDD = 3.15 to 3.45 V; unless otherwise specified VIH VIL Vhys VOH HIGH-level input voltage all digital inputs and I/Os LOW-level input voltage all digital inputs and I/Os Schmitt-trigger hysteresis HIGH-level output voltage standard output; IO = -4 mA 5 ns slew rate output; IO = -4 mA 10 ns slew rate output; IO = -2 mA 20 ns slew rate output; IO = -1 mA 2.0 - 0.4 VDD - 0.4 VDD - 0.4 VDD - 0.4 VDD - 0.4 - - - - - - - - 0.8 - - - - - V V V V V V V 2001 May 07 25 Philips Semiconductors Preliminary specification Digital Signal Processor SAA7715H SYMBOL VOL PARAMETER LOW-level output voltage CONDITIONS standard output; IO = 4 mA 5 ns slew rate output; IO = 4 mA 10 ns slew rate output; IO = 2 mA 20 ns slew rate output; IO = 1 mA I2C-bus output; IO = 4 mA - - - - - - 24 30 - VDD = 3.45 V standard output; CL = 30 pF 5 ns slew rate output; CL = 30 pF 10 ns slew rate output; CL = 30 pF 20 ns slew rate output; CL = 30 pF I2C-bus output; CL = 400 pF - - - - - 60 MIN. - - - - - - TYP. MAX. 0.4 0.4 0.4 0.4 0.4 5 140 100 3.5 200 - - - - 300 UNIT V V V V V A k k pF ns ns ns ns ns ns ILO Rpd Rpu Ci ti(r),ti(f) to(t) output leakage current 3-state outputs internal pull-down resistor to VSS internal pull-up resistor to VDD input capacitance input rise and fall times output transition time VO = 0 V or VDD 50 50 - 6 3.5 5 10 20 - AC characteristics SPDIF1 and SPDIF2 inputs; Tamb = 25 C; VDDA2 = 3.3 V; unless otherwise specified Vi(p-p) Ri Vhys AC input level (peak-to-peak level) input impedance hysteresis of input voltage at 1 kHz 0.2 - - 0.5 6 40 3.3 - - V k mV 2001 May 07 26 Philips Semiconductors Preliminary specification Digital Signal Processor SAA7715H SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Analog DAC outputs; VDDA1 = 3.3 V; fs = 44.1 kHz; Tamb = 25 C; RL = 5 k; all voltages referenced to ground; unless otherwise specified DC CHARACTERISTICS Ro(DAC) Io(max) RL CL Ro(VREFDA) Vo(rms) Vo (THD + N)/S S/N cs PSRR DAC output resistance maximum output current load resistance load capacitance VREFDA output resistance pin 38 pins 34 and 36 (THD + N)/S < 0.1% RL = 5 k - - 3 - - - - at 0 dB at -60 dB code = 0 fripple = 1 kHz; Vripple(p-p) = 1% - - - - - 0.13 0.22 - - 28 3.0 - - 200 - - - - - - - - mA k pF k AC CHARACTERISTICS output voltage (RMS value) unbalance between channels total harmonic distortion plus noise-to-signal ratio signal-to-noise ratio channel separation power supply rejection ratio 1000 0.1 -85 -37 100 80 50 mV dB dB(A) dB(A) dB(A) dB dB 2001 May 07 27 Philips Semiconductors Preliminary specification Digital Signal Processor 14 I2S-BUS TIMING SAA7715H handbook, full pagewidth LEFT WS RIGHT tBCK(H) tr tf th(WS) td(D) tsu(WS) BCK tBCK(L) Tcy LSB MSB tsu(D) th(D) DATA IN DATA OUT LSB MSB MGM129 Fig.9 Timing of the digital audio data inputs and outputs. Table 19 Timing digital serial audio inputs and outputs (see Fig.9) SYMBOL Tcy tr tf tBCK(H) tBCK(L) tsu(D) th(D) td(D) tsu(WS) th(WS) PARAMETER bit clock cycle time rise time fall time bit clock HIGH time bit clock LOW time data set-up time data hold time data delay time word select set-up time word select hold time Tcy = 50 ns Tcy = 50 ns Tcy = 50 ns Tcy = 50 ns Tcy = 50 ns Tcy = 50 ns Tcy = 50 ns Tcy = 50 ns Tcy = 50 ns CONDITIONS - - 0.35Tcy 0.35Tcy 0.2Tcy 0.2Tcy - 0.2Tcy 0.2Tcy MIN. 162 - - - - - - - - - - TYP. - 0.15Tcy 0.15Tcy - - - - 0.15Tcy - - MAX. ns ns ns ns ns ns ns ns ns ns UNIT 2001 May 07 28 Philips Semiconductors Preliminary specification Digital Signal Processor 15 I2C-BUS TIMING SAA7715H handbook, full pagewidth SDA tf tf tLOW tr tSU;DAT tHD;STA tSP tr tBUF SCL tHD;STA tSU;STA tSU;STO S tHD;DAT tHIGH Sr P S MSC610 Fig.10 Definition of timing on the I2C-bus. Table 20 Timing of I2C-bus (see Fig.10) STANDARD MODE I2C-BUS MIN. fSCL tBUF SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition; after this period, the first clock pulse is generated SCL LOW period SCL HIGH period set-up time for a repeated START condition DATA hold time DATA set-up time rise time of both SDA and SCL signals fall time of both SDA and SCL signals set-up time for STOP condition capacitive load for each bus line pulse width of spikes to be suppressed by input filter Cb in pF Cb in pF 0 4.7 - MAX. 100 0 1.3 FAST MODE I2C-BUS UNIT MIN. - MAX. 400 kHz s SYMBOL PARAMETER CONDITIONS tHD;STA 4.0 - 0.6 - s tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO Cb tSP 4.7 4.0 4.7 0 250 - - 4.0 - - - - - - 1000 300 - 400 1.3 0.6 0.6 0 100 - - - 0.9 - s s s s ns ns ns s pF ns 20 + 0.1Cb 300 20 + 0.1Cb 300 0.6 - 0 - 400 50 not applicable 2001 May 07 29 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... andbook, full pagewidth RESERVED1 RESERVED2 100 pF SPDIF2 100 pF SPDIF1 RESERVED3 VDDA1 VDDA2 VSSA1 VSSA2 VDDI1 VSSI1 24 IIS_BCK1 1 IIS_WS1 2 IIS_IN1 3 IIS_IN4 5 25 4 7 8 35 17 23 16 37 15 21 14 10 31 IIS_OUT1 30 IIS_OUT2 XRAM YRAM VSSI2 VDDE VSSE DIV_CLK_IN CLK_IN RTCB SDA A0 SYSCLK SHTCB TSCAN SCL DSP_INOUT7 DSP_INOUT6 DSP_INOUT5 POWERDOWN DSP_RESET 2001 May 07 digital inputs IIS_IN2 6 16 APPLICATION DIAGRAM Philips Semiconductors Digital Signal Processor SPDIF input signals 75 100 nF 75 100 nF 100 nF 100 nF 100 nF 47 F 47 F 10 10 L1 L2 +3.3 V 47 F 29 IIS_OUT3 28 IIS_OUT4 33 IIS_BCK digital outputs SAA7715H DSP CORE 32 IIS_WS 10 k 34 VOUTL 36 VOUTR IIS_IN3 9 STEREO DAC 39 POM 38 VREFDA 47 F 47 F 47 F 10 k 100 100 left output right output microcontroller 4.7 F 100 nF 30 /2 S PRAM PLL DSP CLOCK PROM 256 fs CLOCK TCB I2C-BUS WS_PLL 22 41 44 43 42 40 20 19 26 13 12 11 27 18 +3.3 V +5 V 4.7 k 22 k +5 V 4.7 k 22 k DSP flags 1 F (1) Preliminary specification microcontroller SAA7715H MGT831 (1) Omit this capacitor when a microcontroller is used. microcontroller I2C-bus Fig.11 Application diagram. Philips Semiconductors Preliminary specification Digital Signal Processor 17 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SAA7715H SOT307-2 c y X A 33 34 23 22 ZE e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 (A 3) Lp L A1 e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-08-01 2001 May 07 31 Philips Semiconductors Preliminary specification Digital Signal Processor 18 SOLDERING 18.1 Introduction to soldering surface mount packages SAA7715H If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 Manual soldering This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 18.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 18.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2001 May 07 32 Philips Semiconductors Preliminary specification Digital Signal Processor 18.5 Suitability of surface mount IC packages for wave and reflow soldering methods SAA7715H SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 19 DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable Preliminary data Qualification Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 2001 May 07 33 Philips Semiconductors Preliminary specification Digital Signal Processor 20 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 22 PURCHASE OF PHILIPS I2C COMPONENTS 21 DISCLAIMERS SAA7715H Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2001 May 07 34 Philips Semiconductors Preliminary specification Digital Signal Processor NOTES SAA7715H 2001 May 07 35 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 7 - 9 Rue du Mont Valerien, BP317, 92156 SURESNES Cedex, Tel. +33 1 4728 6600, Fax. +33 1 4728 6638 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: Philips Hungary Ltd., H-1119 Budapest, Fehervari ut 84/A, Tel: +36 1 382 1700, Fax: +36 1 382 1800 India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260, Tel. +66 2 361 7910, Fax. +66 2 398 3447 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553 For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2001 Internet: http://www.semiconductors.philips.com SCA 72 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/01/pp36 Date of release: 2001 May 07 Document order number: 9397 750 07664 |
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